The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically, a semiconductor device including an ESD protection element comprising a MIS transistor including a ballast resistor, and a method of manufacturing the semiconductor device.
The semiconductor devices generally include ESD protection elements for protecting the semiconductor elements from voltage surges due to external ESD (ElectroStatic Discharge), etc. As an ESD protection element is known an ESD protection element using a MIS transistor having a ballast resistor, which functions also as an input/output circuit. Usually, in the MIS transistor including the ballast resistor, the ballast resistor is formed of an impurity doped region continuous to the source/drain region of the MIS transistor.
As one method for realizing the ballast resistor of an impurity doped layer is known the technique called salicide block method (refer to, e.g., Japanese published unexamined patent application No. 2003-133433). In this technique, when the so-called salicide (self-aligned silicide) process is made, the impurity doped layer in the regions for ballast resistors to be formed in is beforehand masked so as not to silicidize the ballast resistor forming regions. Thus, the silicidation on the impurity doped layer is hindered, and the ballast resistors of the impurity doped layer can be formed.
The resistance value of the ballast resistor is an important parameter for determining the ESD breakdown voltage of the ESD protection element, and the breakdown voltage, not only when too low but also when too high, causes discharge ability decrease, heat increase, etc. and must be set at a suitable resistance value.
To this end, conventionally, an impurity doped layer to be the LDD regions of the source/drain is formed in a ballast resistor forming region, and additionally, an impurity doped layer for the resistance value control is formed in the ballast resistor forming region, whereby a ballast resistor having a prescribed resistance value is formed.
However, in the conventional method of manufacturing the semiconductor device described above, the ballast resistor is formed of the impurity doped layer for the LDD regions of the MIS transistor and the impurity doped layer for the resistance value control of the ballast resistor. For this, a series of steps of forming the impurity doped layer must be added, and the manufacturing process is complicated. Structures and manufacturing methods which can control the resistance value of the ballast resistor to be a prescribed value without complicating the manufacturing process have been required.